The present technology relates to a solid-state imaging apparatus and an electronic device employing the apparatus.
In a CMOS (complementary metal-oxide semiconductor) solid-state imaging apparatus, a wire for supplying a voltage to pixels is created in a first wiring layer extended in a vertical or horizontal direction. For more information, refer to documents such as Japanese Patent Laid-open No. 2004-104203.
FIG. 13 is a diagram roughly showing a typical top view of a CMOS solid-state imaging apparatus having a configuration of related art.
As shown in FIG. 13, each pixel includes a photodiode (PD) 51, a floating diffusion (FD) 52 and a transistor (TR) section 53. A number of such pixels are laid out in the vertical and horizontal directions to form a configuration. The transistor section 53 includes an amplify transistor, a select transistor and a reset transistor.
Between the photodiode 51 and the floating diffusion 52, a read gate 54 is provided. A wire 61 is created on the read gate 54.
The floating diffusion 52 and the transistor section 53 are connected to each other by a wire 63 provided on the left side of the photodiode 51. On the left side of the wire 63, a ground wire 64 extended in the vertical direction is provided. The ground wire 64 is connected to a semiconductor base by a contact section 65.
The ground wire 64 receives a ground electric potential also referred to as an earth electric potential from an external source so that the electric potential appearing on the semiconductor base is fixed at the earth electric potential.
The wires 61 and 63 as well as the ground wire 64 are each created as a first wiring layer which is a metallic-wiring layer. The first wiring layer is connected to a second wiring layer, which is also a metallic-wiring layer, through a contact section. However, the connection of the first wiring layer to the second wiring layer is not shown in the figure.